The continued advance of semiconductor technology creates challenging paradoxes. For example, one improvement that has been seen is the reduction in the size of devices incorporated in integrated circuits, while another is the increasing variety and scope of functions designed into integrated circuits. One common effect of the combination of such advances is an increase in both device density and the overall size of integrated circuits. Both effects engender a corresponding increase in the amount of wiring required to interconnect the devices on a given chip. This creates several problems associated with the wiring requirements. One problem is the extent of available die real estate that must be dedicated to the wiring interconnecting the devices. Another problem is the increasing distances between devices.
Experience has shown that one result of increased device density is a corresponding increase in the area of the chip covered by the metal wiring interconnecting those devices. In one example 90% of the surface area of a 0.29 cm.sup.2 chip having 1500 gates is taken up by the wiring metal. The increased density results in reduced spacing between conductive materials, creating a higher risk of capacitive loading. "Capacitive loading" refers to the situation where capacitance between adjacent metal lines is high and a voltage on one of the lines alters the voltage on the other line. The result is a circuit which incorrectly processes information. Capacitive loading is traditionally controlled through maintaining a minimum distance between charge-carrying lines and using resistive materials as spacers between adjacent lines.
In conventional single-level circuit fabrication methods wiring between devices is laid out in straight lines running in either an x- or a y-direction. As the number of devices to be connected increases, connections between any two devices are often longer than the straight line distance between the devices in order to avoid interference between lines connecting other devices. In addition, efficient use of the available space dictates proximal location of a number of the lines to each other, increasing the risk of capacitive loading effects.
One partial solution to the space limitation problem has been to design and fabricate chips with multiple levels for interconnections (see, for example, Stanley Wolf, Silicon Processing for the VLSI Era, Volume 2, 1986, pages 176 and following). Designing a chip as a multi-level device allows a certain percentage of the wiring to be distributed at different wiring levels. However, longer interconnects require thicker wires to keep resistance to a manageable level. Thicker wires, however, exacerbate the problem of reduced separation of conductors at the same or adjoining wiring levels. In an attempt to ameliorate the effects of long interconnects and increased device densities, one partial solution has been developed wherein some portion of the interconnect lines are isolated from surrounding levels by an air region. One such structure is an air bridge, which is fabricated such that the interconnect line is suspended, being completely surrounded by air for some portion of its length. Air regions are formed to provide improved dielectric isolation of adjacent dielectric layers and air-isolated conductive interconnects. One method for fabricating such structures is described in U.S. Pat. No. 5,324,684, issued to Fitch at al. In conventional processing air regions are formed by selectively removing a sacrificial spacer or layer.
The benefits realized from implementing air regions arc limited, however, by certain physical aspects of the air bridge. As the minimum photo dimensions are decreased, the thickness of both the metal and inter-level air insulator must decrease proportionately. Where a wire is suspended in an air region the thinner metal has a greater propensity to sag because it is less rigid. The maximum allowable sag decreases with reduced photo dimensions, however, as it is a function of the inter-level distance. As a result, the maximum length of the air bridge free span will also decrease.
There is often a need to construct air bridges with a clear span of well over 1 centimeter, but conventional photo ground rules limit bridge length. This constraint drastically reduces the wire-ability of circuits being formed. Even air bridges built to the minimum photo ground rules arc limited in length due to mechanical limitations and the effects of resistivity. There remains a need for a procedure to obtain high density air-bridge connections over extended distances (over 1 cm) in the same structure.
There is, in general, one of two types of integrated circuit design rules employed in order to ensure the maximum distance between two points to be connected by an air bridge is always less than the maximum allowable distance. In the first type of design rule, the bridge constraints are established first and then the devices to be connected are positioned according to those constraints. For example, a maximum bridge distance can be established by determining the wiring and air insulation dimensions and setting an appropriate safety factor for the wire sag. Layout rules are then set to constrain the design so that any two points which must be connected are always closer than the calculated maximum bridge distance. The second type of design rule works from the other direction, first positioning devices and then designing air bridge dimensions to meet the maximum distance and sag safety factor requirements. From that information air bridge fabrication parameters such as wire and insulator thickness necessary for each level of interconnect can be identified. Both of these approaches are limited in their effectiveness, however, because they only determine the air bridge characteristics for the worst-case scenario. In either approach, all air bridges for a given integrated circuit are designed to meet the maximum distance requirements. This may unnecessarily limit the performance of a circuit which requires only a few long bridges and has a majority of short bridges. What is needed is a way to better match air bridge fabrication parameters with the circuit requirements.